Classical transistor scaling
ended at 130nm. In all subsequent technology nodes of 90nm, 65nm, 45nm, 32nm  shrinking of transistor degraded the
performance. However, transistor scaling didn’t end at the 130nm. Instead
enhancers were added (strain in 90nm and 65nm, and strain + High-K Metal Gate (HKMG)
in 45nm and 32nm node) 16 to extend Moore’s law. VLSI-CMOS planar devices
especially in 28nm and 20nm are currently the mostly used technologies for mass
production microprocessors and System On-Chip’s (SoC’s) 9. Fig. 1
shows various optimization techniques adopted in semiconductor manufacturing.

Innovative processing techniques
as well as new materials have been introduced such as strained Si, high-k metal
gate and ultra-low-k dielectric 9. Due to an increased gate leakage the old
fashioned SiO2 gate oxide scaling basically stopped at 130nm 9. New methods
were needed to continue device scaling and at the same time not diminishing the
device performance 9.

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