Today’s mobile electronics world is driven byToday’s mobile electronics world is driven by

Today’s mobile electronics world is driven by the devices which
should inherently provide high speed, high performance and low leakage. Such a growing
demand of high performance devices catalyzes the aggressive scaling of the
transistors below 22 nm. However, the incessant miniaturization of transistor dimensions
has resulted in the increased static power dissipation due to the leakage
current at an appalling rate. Moreover, the physical constraints in realizing ultra-scaled
dimensions such as abrupt doping profiles, lithography alignment and the
increased short channel effects due to inefficient gate control have restricted
the realization of the ultra-scaled classical planar transistors. All these factors
have outdistanced the conventional single gate planar transistors thereby shifting
the focus of the researchers towards the multiple-gate transistors which consume
the minimum real-estate on the
semiconductor wafer along with better performance by providing efficient
gate control. In this current


realm, 3D topologies such as Gate-all-around (GAA) nanowires (NW)
are considered to be the most promising ultimate short channel device for
future technology 1-4. However the effective drive current that may be
extracted from a single nanowire is quite low and therefore,  needs to be stacked into arrays consuming the valuable
chip area thereby  countering the
advantage of the scaled dimensions 5,6. Moreover, this effective gate
control leads to a significant overlap of the channel region valence band with
the drain conduction band in the OFF-state regime triggering the lateral band to
band tunneling (L-BTBT) of electrons from the channel to the drain 46-16. However,
the conventional transverse-BTBT (T-BTBT) induced gate induced drain leakage
(GIDL) current arises due to the tunneling of the electrons from the valence
band to the conduction band in the gate-drain overlap region through the
mechanism of band to band tunneling (BTBT) and trap assisted tunneling(TAT) and
is dominant at large negative gate bias 417,18. Therefore, the expedition
of FETs with an enhanced output drive current from 3D topologies along with a
better ION/IOFF ratio has resulted in
the invention of the silicon nanotubes with core shell gate stack 19-27. Such
a nanotube architecture offers the best possible electrostatic gate control
which not only provides immunity to the short channel effects but also results
in a higher drive current due to the efficient volume inversion compared to the
nanowires along with the effective utilization of the real-estate 19-22. However,
this ultimate gate control in the NT architecture results in an enhanced L-BTBT
mechanism due to the presence of the core gate 27. Therefore, the enhanced
L-BTBT in nanotube increases their OFF-state current degrading their ION/IOFF ratio Moreover, the L-BTBT is more pronounced at
the scaled dimensions hindering their scaling to the future technology nodes
and making their usage impractical for high performance computing as well as low
power applications.  Hence, L-BTBT needs
to be mitigated and this problem has been overlooked till date.

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in this work, we propose the use of a dual material gate (DMG) in both the core
as well as outer gate to circumvent the enhanced L-BTBT component in NTFETs to
facilitate their scaling for future technology nodes. The  DMG has been implemented in the past for conventional
lateral channel devices such as planar bulk and SOI MOSFET, TFETs, Junctionless
FETs and nanowire architectures 28-37 and had also been experimentally
realized28313637 for improving the transistor’s performance. However,
for such conventional lateral channel devices, the fabrication of a DMG